1. Field of the Invention
The present invention relates to decimation filters employed for use in an A/D converter that oversamples the analog signal input to the A/D converter. More particularly, the present invention relates to a multiple stage decimation filter that employs cascaded comb filters and a zero insertion filter to provide high attenuation in the stop band to effectively suppress quantization noise and attenuate out-of-band noise, and a steep transition between the pass band and the stop band.
2. The Prior Art
It is common in audio design and in various types of signal processing to employ an A/D modulator in an A/D converter that samples a signal well above the Nyquist rate to obtain a high resolution A/D converter, since it is well known that the resolution of a Nyquist rate A/D converter is limited by the injection of noise from the digital portion of the A/D modulator that is aliased into the passband. Further, a Nyquist rate A/D converter requires effective anti-aliasing filters, high performance sample and hold circuits and jitter free timing.
An A/D modulator that samples the analog input signal at a rate well above the Nyquist rate is termed an oversampling A/D modulator. Though different type of oversampling A/D modulators are known, a widely employed oversampling A/D modulator is the delta-sigma modulator. The delta-sigma modulator is often employed because it may be implemented using relatively simple and high-tolerance analog components, while maintaining good linearity because the delta-sigma modulator typically employs single-bit quantization.
In the A/D converter, the A/D modulator oversamples the analog signal at a frequency well above the Nyquist rate to form short digital words, and the decimator inputs these short words, and down samples them to form an output of longer words at the Nyquist rate. Processing signals at the Nyquist rate is well known and understood by those of ordinary skill in art, and accordingly will not be described herein in detail, however, it should be appreciated that the Nyquist frequency is twice the cutoff frequency for the signal being sampled.
Because the sample rate of the over-sampled A/D modulator is requires complex circuitry for signal processing, the bit stream form the A/D modulator is commonly decimated by a decimation filter to provide a sample rate that can be more readily processed. The downsampling order of the decimation, D, is the ratio of the oversampling frequency, Fs, to the Nyquist frequency, Fn. For an A/D converter employing an oversampled A/D modulator, the decimation filter should have a steep transition between the passband and the stopband to avoids the use of an anti-aliasing analog filter on the front end of the A/D converter. Further, the decimation filter should suppress or attenuate noise.
There are typically two types of noise that the decimation filter must suppress or attenuate. These are quantization noise and out-of-band noise or signal. Quantization noise is created by the A/D modulator in the transformation of the analog input to the digital output, and is considered by those of ordinary skill in the art as an error signal. Quantization noise is typically quite minimal in the base band, however, quantization noise can become quite severe in higher frequency bands above the base band. Out-of-band noise and signal are signals occurring at a frequency that is outside the selected frequency range of the analog signal that is being converted to a digital signal.
To meet these criteria in the decimation filter, a one stage finite impulse response filter (FIR) or a one stage infinite impulse response filter (IIF) is quite complicated and difficult to implement. A multi-stage, multi-rate decimation filter as an efficient manner of implementing the decimation filter has been proposed by Karema, et al. xe2x80x9cAn Oversampled Sigma-Delta Converter Circuit Using Two-Stage Fourth Order Modulatorxe2x80x9d, IEEE Proceedings ISCAS ""90, pp. 3279-3282, May 1990.
Karema et al. discloses a two-stage decimation filter. The first stage in the decimation filter employs a cascade of comb filters with a length of D0, D0+1 or D0+2, for the decimation of the oversampled bit stream to 4Fn or 2Fn. As is well understood by those of ordinary skill in the art, the length D0 is the downsampling order of the first stage and is commonly equal to D/4 or D/2. As described above, D represents the overall downsampling order of the decimation, and is the ratio of Fs to Fn. The cascade of comb filters is relatively simple and provides attenuation in the stopband. The second stage of the decimation filter is a quarter band or half band filter that requires relatively less restriction on the stop band, but requires a steep transition. The second stage of the decimation filter is more complicated to implement than the first stage.
Although known decimation filters provide some amount attenuation in the stopband and some degree of steepness in transition between the stopband and the passband, there exists a need for greater attenuation in the stopband and a greater degree of steepness between the stopband and the passband than is presently provided in the art. Further, there also exists a need to realize the implementation of the decimation filter in very efficient manner to reduce the silicon area in an integrated circuit required by the decimation filter.
According to the present invention, a decimator is implemented as a filter having high attention in the stop band and a steep transition between the stop band and the pass band of the decimation filter. The high attenuation in the stop band and a steep transition between the stop band and the pass band of the filter implementing the decimator are desired to prevent the quantization noise and out-of-band noise or signal from aliasing back into the base band after the high sample rate output from the A/D modulator is down sampled by the decimator.
According to the present invention, a decimator includes a zero insertion filter having an input and an output, wherein the input forms an input of the decimation filter. The input to the zero insertion filter is a 1-bit input stream oversampled at 1.28 MHz. The output of the zero insertion filter is a 6-bit word at a sample rate of 1.28 MHz. The output of the zero insertion filter is coupled to a cascade of four comb filters having a first accumulator stage and a second stage having a first differentiator portion and second differentiator portion wherein the first stage has an input coupled to the output of the zero insertion filter and an output, the first differentiator portion has an input coupled to the output of the first stage and an output, and the second differentiator portion has an input coupled to the output of the first differentiator portion and an output. A down sampling of 32 occurs in the first accumulator stage to provide a 31-bit word at a sample rate of 40 KHz. A down sampling of 2 occurs in the first differentiator portion of the second stage to provide a 31-bit word at a sample rate of 20 KHz. The output of the second differentiator portion of the second stage is a 26-bit word at a sample rate of 20 KHz. A frequency shaping filter having an input and an output, wherein the input is coupled to the output of the second differentiator portion, performs a 26-bit addition and substraction to provide a 16-bit output that forms an output of the decimation filter,
According to another aspect of the present invention, the zero insertion filter includes a serial shift register and an adder. The serial shift register is implemented as a four phase delay line to reduce the number of storage units in the serial shift register that are required for a given number of delay time periods. In the four phase delay line for serial shift register there are storage cells which are divided sequentially into groups of three storage cells. After each group of three storage cells, a free storage cell is disposed. Four non-overlapping clock signals CLK0, CLK1, CLK2, and CLK3 are provided to each of the storage cells and the free storage cells, respectively. By employing a four phase delay line to implement the serial shift register, rather than the more common two-phase delay line that includes a free storage cell between each storage cell, the amount of integrated circuit area required to implement the serial shift register is significantly reduced.